Slip Sec Error How to solve?

rodrigofck · ‎08-02-2007

I?m having a slip sec error. Somebody knows how can i solve this problem? Thanks A lot!

#sh run

!

controller E1 0/1

framing NO-CRC4

ds0-group 1 timeslots 1-15,17-31 type r2-digital r2-compelled ani

cas-custom 1

country brazil

metering

answer-signal group-b 1

!

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#sh controllers e1

E1 0/1 is up.

Applique type is Channelized E1 - balanced

No alarms detected.

alarm-trigger is not set

Version info Firmware: 20051006, FPGA: 20, spm_count = 0

Framing is NO-CRC4, Line Code is HDB3, Clock Source is Line.

CRC Threshold is 320. Reported from firmware is 320.

Data in current interval (29 seconds elapsed):

0 Line Code Violations, 0 Path Code Violations

3 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins

3 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs

Total Data (last 82 15 minute intervals):

1 Line Code Violations, 1088 Path Code Violations,

8646 Slip Secs, 0 Fr Loss Secs, 1 Line Err Secs, 0 Degraded Mins,

8647 Errored Secs, 0 Bursty Err Secs, 1 Severely Err Secs, 101 Unavail Secs

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#sh ver

Compiled Tue 28-Feb-06 23:31 by alnguyen

ROM: System Bootstrap, Version 12.2(8r) [cmong 8r], RELEASE SOFTWARE (fc1)

TelefoniaIP_Eng_Comercial_SC uptime is 1 day, 17 hours, 30 minutes

System returned to ROM by error - a SegV exception, PC 0x81CC5978 at 16:44:08 GM

T Mon Jul 30 2007

System restarted at 16:48:34 GMT Mon Jul 30 2007

System image file is "flash:c2600-ipvoice-mz.124-7.bin"

Cisco 2610XM (MPC860P) processor (revision 4.1) with 118784K/12288K bytes of mem

ory.

Processor board ID FTX0945A2UL

M860 processor: part number 5, mask 2

1 FastEthernet interface

1 Serial interface

1 Channelized E1/PRI port

1 ATM/Voice AIM

32K bytes of NVRAM.

32768K bytes of processor board System flash (Read/Write)

Configuration register is 0x2102

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Report Inappropriate Content · ‎08-08-2007

I think Slips are usually caused by a clocking issue on the line. The clock source on your line is set for

line. Have you verified with the provider that they are providing clocking on the line? I am also

seeing AAL5 CRC errors on the subinterface of the ATM interface. These may be contributing to the SLIPS or vice-versa. The CRC errors could be caused by any one of the following:

Dropped cells due to traffic policing in the ATM cloud on one or more VCs attached to the ATM

interface.Noise, gain hits, or other transmission problems on the data-link equipment.

For more information please click following URL:

http://www.cisco.com/en/US/products/sw/iosswrel/ps1828/products_system_message_guide_chapter09186a0080080f7c.html#wp1025806