------------------ show controllers e1 ------------------
E1 0/3/0 is up.
Applique type is Channelized E1 - balanced
No alarms detected.
alarm-trigger is not set
Version info Firmware: 20071009, FPGA: 20, spm_count = 0
Framing is CRC4, Line Code is HDB3, Clock Source is Line.
CRC Threshold is 320. Reported from firmware is 320.
Data in current interval (651 seconds elapsed):
0 Line Code Violations, 0 Path Code Violations
6 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins
6 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
Total Data (last 4 15 minute intervals):
1 Line Code Violations, 3 Path Code Violations,
37 Slip Secs, 0 Fr Loss Secs, 1 Line Err Secs, 0 Degraded Mins,
40 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
