02-29-2008 07:54 PM - edited 03-03-2019 08:55 PM
I'm confused...always...
If someone could shed light on clock changes on atm interfaces, what they really mean...I originally thought that it was pointing to a faulty wic, however I just replaced a wic and am getting the same trouble...eventually the interface will flaps or has a bgp state change which causes a trap...
Any assistance is appreciated.
03-01-2008 04:12 AM
Please poste the relevant error messages, "show controllers", etc.
03-01-2008 10:42 AM
not a lot of space i'll have to upload more in a bit...
*Aug 19 15:46:00 UTC: %ATM-5-UPDOWN: Interface ATM1/0.1033, Changing autovc 0/33 to PVC activated.
*Aug 19 15:46:24 UTC: clock change done for int ATM1/0
*Aug 19 15:46:25 UTC: clock change removed for int ATM1/0
*Aug 19 15:46:31 UTC: %BGP-5-ADJCHANGE: neighbor 172.16.26.1 Up
*Aug 19 15:48:57 UTC: clock change done for int ATM1/0
*Aug 19 15:48:58 UTC: clock change removed for int ATM1/0
*Aug 19 15:49:38 UTC: clock change done for int ATM1/0
*Aug 19 15:49:39 UTC: clock change removed for int ATM1/0
*Aug 19 15:53:39 UTC: clock change done for int ATM1/0
*Aug 19 15:53:40 UTC: clock change removed for int ATM1/0
*Aug 19 15:54:18 UTC: clock change done for int ATM1/0
*Aug 19 15:54:19 UTC: clock change removed for int ATM1/0
*Aug 19 15:55:07 UTC: clock change done for int ATM1/0
*Aug 19 15:55:08 UTC: clock change removed for int ATM1/0
*Aug 19 15:56:50 UTC: clock change done for int ATM1/0
*Aug 19 15:56:51 UTC: clock change removed for int ATM1/0
*Aug 19 15:58:06 UTC: clock change done for int ATM1/0
*Aug 19 15:58:07 UTC: clock change removed for int ATM1/0
*Aug 19 16:12:00 UTC: clock change done for int ATM1/0
*Aug 19 16:12:02 UTC: clock change removed for int ATM1/0
*Aug 19 16:14:47 UTC: clock change done for int ATM1/0
*Aug 19 16:14:48 UTC: clock change removed for int ATM1/0
*Aug 19 16:15:26 UTC: clock change done for int ATM1/0
*Aug 19 16:15:27 UTC: clock change removed for int ATM1/0
*Aug 19 16:16:03 UTC: clock change done for int ATM1/0
*Aug 19 16:16:04 UTC: clock change removed for int ATM1/0
*Aug 19 16:23:08 UTC: clock change done for int ATM1/0
*Aug 19 16:23:09 UTC: clock change removed for int ATM1/0
*Aug 19 16:38:12 UTC: clock change done for int ATM1/0
*Aug 19 16:38:13 UTC: clock change removed for int ATM1/0
*Aug 19 16:47:20 UTC: clock change done for int ATM1/0
*Aug 19 16:47:21 UTC: clock change removed for int ATM1/0
*Aug 19 17:12:44 UTC: clock change done for int ATM1/0
*Aug 19 17:12:45 UTC: clock change removed for int ATM1/0
*Aug 19 17:15:47 UTC: clock change done for int ATM1/0
*Aug 19 17:15:48 UTC: clock change removed for int ATM1/0
*Aug 19 17:16:25 UTC: clock change done for int ATM1/0
*Aug 19 17:16:26 UTC: clock change removed for int ATM1/0
*Aug 19 23:36:27 UTC: clock change done for int ATM1/0
*Aug 19 23:36:28 UTC: clock change removed for int ATM1/0
*Aug 20 00:00:54 UTC: clock change done for int ATM1/0
*Aug 20 00:00:55 UTC: clock change removed for int ATM1/0
*Aug 20 00:02:23 UTC: clock change done for int ATM1/0
*Aug 20 00:02:24 UTC: clock change removed for int ATM1/0
*Aug 20 00:02:41 UTC: clock change done for int ATM1/0
*Aug 20 00:02:42 UTC: clock change removed for int ATM1/0
*Aug 20 00:04:48 UTC: clock change done for int ATM1/0
*Aug 20 00:04:49 UTC: clock change removed for int ATM1/0
*Aug 20 00:05:26 UTC: clock change done for int ATM1/0
*Aug 20 00:05:27 UTC: clock change removed for int ATM1/0
*Aug 20 00:07:34 UTC: clock change done for int ATM1/0
*Aug 20 00:07:35 UTC: clock change removed for int ATM1/0
*Aug 20 00:11:55 UTC: clock change done for int ATM1/0
*Aug 20 00:11:56 UTC: clock change removed for int ATM1/0
*Aug 20 00:12:47 UTC: clock change done for int ATM1/0
*Aug 20 00:12:48 UTC: clock change removed for int ATM1/0
*Aug 20 00:23:45 UTC: clock change done for int ATM1/0
*Aug 20 00:23:46 UTC: clock change removed for int ATM1/0
*Aug 20 02:47:05 UTC: clock change done for int ATM1/0
*Aug 20 02:47:06 UTC: clock change removed for int ATM1/0
03-01-2008 10:45 AM
Interface ATM1/0 is up
Hardware is RS8234 ATM DS3
LANE client MAC address is
hwidb=0x84ED586C, ds=0x84ED7358
RS8234 base 40800000, ds 84ED7358, PM5346 base 40C00000, slave base 40C00000
SBDs - avail 2048, guaranteed 1, unguaranteed 2047, starved 0 rbds 4098
Queue TXQ Addr Pos StQ Addr Pos
0 UBR 40848F00 0 079C01A0 0
1 UBR PLUS 40849300 0 079C09A0 0
2 UBR TUN1 40849700 0 079C11A0 0
3 UBR TUN2 40849B00 0 079C19A0 0
4 UBR TUN3 40849F00 0 079C21A0 0
5 ABR 4084A300 0 079C29A0 0
6 VBR NRT 4084A700 49 079C31A0 49
7 VBR RT 4084AB00 0 079C39A0 0
8 VBR/ABR TUN1 4084AF00 0 079C41A0 0
9 VBR/ABR TUN2 4084B300 0 079C49A0 0
10 VBR/ABR TUN3 4084B700 0 079C51A0 0
11 SIG 4084BB00 0 079C59A0 0
12 CBR 4084BF00 0 079C61A0 0
13 VPD 4084C300 0 079C69A0 0
Queue FBQ Addr Pos RSQ Addr Pos
0 OAM 4095B180 255 079C7260 0
1 UBR 4095C180 0 079C8260 0
2 UBR PLUS 4095D180 0 079C9260 0
3 UBR TUN1 4095E180 0 079CA260 0
4 UBR TUN2 4095F180 0 079CB260 0
5 UBR TUN3 40960180 0 079CC260 0
6 ABR 40961180 0 079CD260 0
7 VBR NRT 40962180 178 079CE260 172
8 VBR RT 40963180 0 079CF260 0
9 VBR/ABR TUN1 40964180 0 079D0260 0
10 VBR/ABR TUN2 40965180 0 079D1260 0
11 VBR/ABR TUN3 40966180 0 079D2260 0
12 SIG 40967180 0 079D3260 0
13 CBR 40968180 0 079D4260 0
PCI bus err 0, DMA fifo full err 0, RSM parity err 0
RSM sync err 0, RSM/SEG Q full err 0, RSM overflow err 0
Framer Chip Type PM7345
Framer Chip ID 0x20
Framer State RUNNING
Defect Status NO ERRORS
Loopback Mode NONE
Clock Source INTERNAL (but the source of this clock is derived from LINE)
DS3 Scrambling ON
Framing DS3 C-bit w/PLCP framing
TX cells 7626782
TX bytes 404219446
Last output time 15:02:32
RX cells 20976
RX bytes 180262858
Last input time 15:02:32
Line Code Violations (LCV) 0
DS3: F/M-bit errors 4831
DS3: parity errors 314
DS3: path parity errors 296
DS3/E3: G.832 FEBE errors 893
T3/E3: excessive zeros 0
PLCP BIP errors 4258
PLCP framing octet errors 32835
PLCP FEBE errors 1790
uncorrectable HEC errors 10847
idle/unassigned cells dropped 0
LCV errored secs 0
DS3: F/M-bit errored secs 191
DS3: parity errored secs 172
DS3: path parity errored secs 166
T3/E3: excessive zeros errored secs 0
DS3/E3: G.832 FEBE errored secs 191
PLCP BIP errored secs 192
PLCP framing octet errored secs 191
PLCP FEBE errored secs 153
uncorrectable HEC errored secs 192
LCV error-free secs 53963
DS3: F/M-bit error-free secs 53772
DS3: parity error-free secs 53791
DS3: path parity error-free secs 53797
T3/E3: excessive zeros error-free secs 53963
DS3/E3: G.832 FEBE error-free secs 53772
PLCP BIP error-free secs 53771
PLCP framing octet error-free secs 53772
PLCP FEBE error-free secs 53810
uncorrectable HEC error-free secs 53771
03-01-2008 10:46 AM
i will post more later today, have to get the wife from work...
thanks for you interest and assistance.
03-01-2008 11:03 AM
hi, looks like your DS3 circuit has errors, you can compare show controllers e3, likely some error counter increase at the time toy get the clock change message.
Hope this helps, please rate post if it does!
03-01-2008 01:33 PM
Thanks for the help, I noticed that as well, but what about the clocking being internal? That doesn't make sense...
03-01-2008 03:00 PM
Probably the explanation is in some internal of the driver, like this line hints to:
Clock Source INTERNAL (but the source of this clock is derived from LINE)
Bottom line, as long you do not have configure clock source internal under controller T3, you're fine.
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