Output buffers in access switches?

Unanswered Question
Jan 18th, 2010

I just went through the Networkers slides for the catalyst 3750 and 3750E.  I'm looking for information on the amount of packet memory that is available to help with speed conversion when traffic enters the switch on a 10 Gig port and exits on a lower speed port.  I can find a lot of information on the percentage allocations but nothing that tells me how much memory there is.  It looks like each port ASIC manages its own output buffers and that however much there is gets shared amoung all the ports common to each port ASIC.  But, how do I find out how much there is?  It would also be good to know if it is managed as particles -- each packet gets what it needs -- or if it is preallocated into MTU sized chunks.

This question is much easier for the Catalyst 6500 than for the shared memory access switches.

Thanks

jim warner

UC Santa Cruz

I have this problem too.
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Ganesh Hariharan Mon, 01/18/2010 - 23:28

Hi Jim,

For undestanding about the output buffer and tuning check out the below link hope that clear out your query!!

Understanding Buffer misses and failures:-

http://www.cisco.com/en/US/products/hw/modules/ps2643/products_tech_note09186a0080093fc5.shtml

Buffer tuning document:-

http://www.cisco.com/en/US/products/hw/routers/ps133/products_tech_note09186a00800a7b80.shtml

If helpful do rate the valauble post

Regards

Ganesh.H

jwarner Thu, 01/21/2010 - 09:09

Interesting reading. But I think the second article you site makes it

clear that

"buffers" in this context means structures used to pass packets to the CPU.

I'm not interested in processor switching. I want to know how much packet

memory is available in a shared memory switch design like the Cat 3750.

What I should do to fix not having enough would be interesting, but I

think I need to know how much there is first.

Quoting from the 2nd article:

The input and output drops are due to the input and output queues

being overrun by a burst of traffic. This is not related to a buffer

problem, but rather to a process switching performance limitation.

How big a burst can be handled will be determined by the amount of memory

available. And that's my question.

tonypearce1 Wed, 09/07/2011 - 01:36

Hi,

Excuse me for bringing up an old post but I too am looking for the same information that you mention in your posts. I was wondering if you ever did find a suitable answer to your questions as I am looking to do the same with my 3750's? All of the documentation I can find either relates to routing or to higher end switches. There is very little with regards to buffers on 3750 type switches.

Regards,

Tony.

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