03-24-2010 09:30 AM - edited 03-06-2019 10:17 AM
c7300#sh c7300
Slot Card Type Status Insertion time
---- --------- ------ --------------
0,1 NSE100 Up 47w4d ago
2 2PA Carrier Card Active 47w4d ago
4 7304-MSC-100 Active 47w4d ago
5 7304-MSC-100 Active 47w4d ago
FPGA information:
Hardware FPGA version
Slot Card Type Version Bundled Flash Current
---- --------- -------- ------- ------- -------
*0 NSE100 (MB) 05.01 01.14 01.08 01.08
0 NSE100 (DB) 05.01 01.08 01.08 01.08
2 2PA Carrier Card 02.00 01.40 01.40 01.40
4 7304-MSC-100 01.01 00.27 00.27 00.27
5 7304-MSC-100 01.01 00.27 00.27 00.27
* - Card needs an FPGA update
# - Card needs to be reloaded for the new FPGA to take effect
Shared Port Adapter information:
Slot/Subslot SPA Type Status Insertion time
------------ -------- ------ --------------
4/0 2xGE SPA ok 27w2d ago
4/1 not present missing never
5/0 1xOC12 POS SPA ok 47w4d ago
5/1 not present missing never
Port Adapter Information
Slot PA Type Status Insertion time
---- --------- ------ --------------
2 PA-2T3+ Active 47w4d ago
Based on the output above my quetion is the above output shows that the NSE100 card in slot 0 needs an FPGA update by have (*) next to the card!
Can you please correct if i'm wrong by saying that If the FPGA versions of the Active NSE in slot0 do not match and the NSE is slot 1 and failover to the standby NSE, then we could experience problem and we may be required to upgrade the FPGAs on the standby NSE?
Also i understand that thw FPGA is just a memory built in on hardware for the C7300)
Francisco.
03-24-2010 12:02 PM
Hello Francisco,
an FPGA is a Field Programmable Gate Array in other words logic circuits that can be programmed and updated.
It is not a memory.
They are part of a form of HW assisted forwarding for this specific type of processor so they are important.
As you noted they need to be in sync between the two NSE-100 network processors.
This makes this platform to stand in the middle between SW based routers and multilayer switches (that use ASIC chips that cannot be updated via software as FPGA)
see
http://www.cisco.com/en/US/docs/ios/12_1/12_1ex/feature/guide/73fpga.html#wp1024396
Hope to help
Giuseppe
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