A router with multiple Primary Rate Interfaces (PRIs) can experience slip errors on one of the T1 PRIs. This happens when you have multiple clock sources.
If slips are present on the T1 line, there is a clocking problem.
The Customer Premises Equipment (CPE) needs to synchronize to the clocking from the T1 provider (telco).
For example, in a 2821, the HWIC slots where the VWIC card inserted is part of the Motherboard clocking domain. This domain has 1 Phase-Lock-Loop (PLL), which acts as the internal clock to the TDM backplane on the router. The PLL can only lock on to one external source of clocking and in your case, you have two external sources. One source comes from T1 0/0/0 and the other comes from 0/0/1. If these two external sources are not synchronized on the Telco side, then one source always experiences slips.
The RX Buffer on controller 0/0/1 receives the clock from the line or telco.
The PLL receives the clock from 0/0/1 since you have the network-clock-selectstatement configured for 0/0/1 with priority 1.
The TX buffer receives clocking from the PLL, which results in no slips and a clean interface for PRI 0/0/1.
The RX buffer on the 0/0/0 interface receives clocking from the line since the Telco switch sends clocking.
The TX buffer on the 0/0/0 interface receives clocking from the PLL since network-clock-participate is configured. If this happens, the RX and TX buffers receive clocking from two different sources and you then get slips and errors on the line. The removal of the network-clock-participate command is not an option as this is required to configure a PRI.
In order to fix this, try these options:
Use the NM-HDV, since NM-HDV have their own built in PLL, in order to create a separate clocking domain.
Move the connections from each switch to the same router. That way, both connections to the gateway come from the same Telco switch and the external clocking on both connections are synced and there are no slips.