4500-X Port to Asic

[Pim Scheffers]

Hi There,

Does anyone have a link to an overview of the Port to Asic configuration of the Cisco Catalyst 4500-X

I was watching a recorded cisco live presentation and the attached slide came up. (look at bullet point 4)

Unfortunately the presenter did not talk at all about that bullet point.

I really want to know which ports groups are bundeld to which asic.

[aukhadiev]

Hi,

you can view this presentation - BRKARC-3446 - Cisco Catalyst 4500-X Switch Architecture (2012 San Diego) - at www.ciscolive365.com:https://www.ciscolive365.com/connect/sessionDetail.ww?SESSION_ID=4132

To view registration is required, but it is free and it will not take much of your time ...In any case, I will attached the slide with the information you are interested in...

[rickr007]

This link no longer works.

Can anyone share the entire presentation to me?

kc6alg@gmail.com

Thanks,

rickr

[ladopetrucci]

Hi 

could you please sent me this hole presentation BRKARC-3446

thank you very much

ladoninikashvili@gmail.com

[epesce]

https://www.ciscolive.com/c/dam/r/ciscolive/us/docs/2012/pdf/BRKARC-3446.pdf

[Marvin Rhoads]

Besides the presentation (good link), you can also use the command "show platform mapping ports"

Look at the "portset" column in the resultant output:

#show platform mapping ports

Executing the command on VSS member switch role = VSS Active, id = 1

Interface  Superport  Subport  CompactSubportId  PortSet  Phyport  Aggport    PimPhyport

Te1/1/1    60         0        12                15       12       56         48       

Te1/1/2    61         0        14                15       14       Po20(852)  49       

Te1/1/3    66         0        16                17       16       58         50       

Te1/1/4    67         0        18                17       18       59         51       

Te1/1/5    68         0        20                18       20       60         52       

Te1/1/6    69         0        22                18       22       61         53       

Te1/1/7    70         0        24                19       24       62         54       

Te1/1/8    71         0        26                19       26       63         55       

Te1/1/9    44         0        28                11       28       64         56       

Te1/1/10   45         0        30                11       30       65         57       

Te1/1/11   56         0        32                14       32       66         58       

Te1/1/12   57         0        34                14       34       67         59       

Te1/1/13   52         0        36                13       36       68         60       

Te1/1/14   53         0        38                13       38       69         61       

Te1/1/15   64         0        40                16       40       Po1(833)   62       

Te1/1/16   65         0        42                16       42       Po1(833)   63       

Te1/1/17   32         0        44                8        44       72         64       

Te1/1/18   33         0        46                8        46       73         65       

Te1/1/19   36         0        48                9        48       74         66       

Te1/1/20   37         0        50                9        50       75         67       

Te1/1/21   40         0        52                10       52       76         68       

Te1/1/22   41         0        54                10       54       77         69       

Te1/1/23   48         0        56                12       56       78         70       

Te1/1/24   49         0        58                12       58       79         71

[Pim Scheffers]

Thanks, both your replies were very helpfull

[Marvin Rhoads]

You're welcome. Please rate helpful replies and/or mark your question as answered to help improve community content.

[Zaaf Aba]

Thanks for the command

But which column in the output shows the ASIC number?

WS-C4500X-32__1#show platform mapping ports
Interface  Superport  Subport  CompactSubportId  PortSet  Phyport  Aggport    PimPhyport
Te1/1      60         0        8                 15       12       56         48
Te1/2      61         0        10                15       14       57         49
Te1/3      66         0        12                17       16       58         50
Te1/4      67         0        14                17       18       59         51
Te1/5      68         0        16                18       20       60         52
Te1/6      69         0        18                18       22       61         53
Te1/7      70         0        20                19       24       62         54
Te1/8      71         0        22                19       26       63         55
Te1/9      44         0        24                11       28       64         56
Te1/10     45         0        26                11       30       Po3(91)    57
Te1/11     56         0        28                14       32       Po3(91)    58
Te1/12     57         0        30                14       34       67         59
Te1/13     52         0        32                13       36       68         60
Te1/14     53         0        34                13       38       69         61
Te1/15     64         0        36                16       40       70         62
Te1/16     65         0        38                16       42       71         63
Te1/17     32         0        40                8        44       72         64
Te1/18     33         0        42                8        46       73         65
Te1/19     36         0        44                9        48       74         66
Te1/20     37         0        46                9        50       75         67
Te1/21     40         0        48                10       52       76         68
Te1/22     41         0        50                10       54       77         69
Te1/23     48         0        52                12       56       78         70
Te1/24     49         0        54                12       58       79         71

Interface  Superport  Subport  CompactSubportId  PortSet  Phyport  Aggport    PimPhyport
Te1/25     16         0        56                4        60       80         72
Te1/26     17         0        58                4        62       81         73
Te1/27     20         0        60                5        64       82         74
Te1/28     21         0        62                5        66       83         75
Te1/29     24         0        64                6        68       84         76
Te1/30     25         0        66                6        70       85         77
Te1/31     28         0        68                7        72       86         78
Te1/32     29         0        70                7        74       87         79

Interface    Superport  Subport  CompactSubportId  PortSet  Phyport  Aggport
Cpu phyport  72         0        0                 20       4        Cpu aggport(0)
Cpu phyport  72         1        0                 20       5        Cpu aggport(1)
Cpu phyport  72         2        2                 20       6        Cpu aggport(2)
Cpu phyport  72         3        2                 20       7        Cpu aggport(3)
Cpu phyport  72         4        4                 20       8        Cpu aggport(4)
Cpu phyport  72         5        4                 20       9        Cpu aggport(5)
Cpu phyport  72         6        6                 20       10       Cpu aggport(6)
Cpu phyport  72         7        6                 20       11       Cpu aggport(7)

The column PortSet lists ASIC numbers. I did some sorting etc and total unique numbers for front panel ports were 16, which means two font panel ports are mapped to one ASIC

But the ASIC numbers start from 4 and goes upto 19 for front panel ports? does anyone know why, is it because of how it is on this platform?

ASIC number 20 is shown against Cpu phyport

Thanks