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New Member

Slips secs + E1 issue

Hi,

I have an issue with slip secs on a 2811 with a VWIC-1MFT-E1 card, I have tried setting the clock source to internal as well as line but this issue remains, any ideas? thanks

E1 0/0/0 is up.

Applique type is Channelized E1 - balanced

No alarms detected.

alarm-trigger is not set

Version info Firmware: 20041023, FPGA: 16, spm_count = 0

Framing is CRC4, Line Code is HDB3, Clock Source is Internal.

CRC Threshold is 320. Reported from firmware is 320.

Data in current interval (574 seconds elapsed):

0 Line Code Violations, 0 Path Code Violations

14 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins

14 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs

Total Data (last 24 hours)

0 Line Code Violations, 0 Path Code Violations,

2530 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins,

2530 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs

1 ACCEPTED SOLUTION

Accepted Solutions
jmn
New Member

Re: Slips secs + E1 issue

Hello,

This wil be the sollution for You.

network-clock-participate wic 0

network-clock-select 1 E1 0/0/0

Regards,

Jan Meeling

Technical Support Specialist

Getronics PinkRoccade

1 REPLY
jmn
New Member

Re: Slips secs + E1 issue

Hello,

This wil be the sollution for You.

network-clock-participate wic 0

network-clock-select 1 E1 0/0/0

Regards,

Jan Meeling

Technical Support Specialist

Getronics PinkRoccade

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