I haven't tested it, but it should be possible. Relevant issues at this point would be: clock source, clock rate, and encapsulation.
For simplicity, keep the encapsulation at the default HDLC.
Clock source: there can only be one source of clocking on the circuit, and it's the side that's DCE (in this case, the 805.)
Clock rate: on the DCE (805) side, set the clock rate to 512k with the command:
CLOCK RATE 512000
The DTE side (5300) should detect the slower clocking, and accept the connection.