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Causes of Buffer overruns?

Buffer overruns?

A trainee NE has asked me this question and I'm finding it difficult to find a suitable answer.

After DRAM where would buffer overruns occur on a router as a result of

- the router bus OR the processor OR the route processor OR the interface hardware

(Specifically he knows lack of DRAM is the main area in which overruns are caused)

I'm inclined to go for the processor as this is mostly closely linked to DRAM which is the main cause.

Anyone have any ideas?

Thanks

Ed

Network Enginneer

Axians

1 REPLY
Bronze

Re: Causes of Buffer overruns?

This was documented elsewhere on CCO -

Overruns appear in the output of the show interface Serial 0 command when the serial receiver hardware is unable to hand received data to a hardware buffer because the input rate exceeds the receiver's ability to handle the data.

This occurs due to a limitation of the hardware. Overruns occur when the internal First In, First Out (FIFO) buffer of the chip is full, but is still trying to handle incoming traffic. The serial controller chip

has limited internal FIFO.

Some chips, for example, have only 256 bytes of buffer space. Data from the network will be received into the buffer, whereupon the chip will attempt to move the data from the buffer to the router's shared memory for the CPU to process. If the chip is not able to move the data from its internal FIFO buffer into shared memory faster than the rate at which data is received on the interface, then the internal

FIFO buffer will be full, incoming data will be dropped, and the overrun counter will be incremented.

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