There is a question about implementing the CEF technology in Catalyst 3550 series switches. I found neither proof nor disproof (at cisco.com data sheets) for the switch ASIC has its own forwarding engine (FE) and, hence, is able to perform the distributed CEF technology. It's important for me 'cause I'm making performance comparsions for different architechtures. Thanks.
I don't think that SMI would handle some more features that EMI :)
But I'm not sure whether the Catalyst is dCEF-capable by default and the feature has no the disabling IOS commands at all.
From the one hand the 3550 switches use the "shared memory fabric" architecture and, hence, it's more slow solution 'cause the CPU is involved into controlling the shared buffer. I see no use to implement the dCEF.
From the other hand I found presentations about Catalyst architectures where forwarding desision (on Cat.3550) was made on the ingress ASIC. That would mean that the process of making "forwarding desision" is ASIC - personalized and, hence, dCEF is implemented.
I think that there must be an architecture documents that explain clearly the forwarding process of the 3550 Catalysts.
I know that the 6500's are capable to dCEF, but the 3750's are also doing that.
I've been comparing 3550's and 3750's and one of my tasks is to say what architecture is more powerful and cost-saving at co-relating models. dCEF is one of the central features that would affect the overall switch performance when there is hard traffic. So I need to know exactly is there CEF or dCEF.
Had I needed to test the performance I'd say that the either 3550 or 3750 runs faster and that is all what we need... But I gotta find the architecture explaination for building 3750 instead of 3550. I think that it wasn't enough to rise the CPU frequency to 700MHz and add the StackWise ring.
So, I need to say like:"If you choose xxxx model then you have the dCEF technology and so you can be sure, that implementing huge ACLs, policies and QoS won't overload the CPU as it could be in the case of implementing CEF". The 3750 uses the dCEF (it's the fact), that can be disabled back to CEF.
The question is about 3550... If the dCEF is present then the 3750 port ASICs have no advantages before 3550 ones. If 3550 have the CEF then 3750 port ASICs were significantly improved...
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