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Multiple PRI ports clocking issue

Hello,

We have a 3845 with 2 VWIC2-2MFT-G703 cards. The router is between Telcos and another 3945. 
This router acts as a forwarder, fax gateway, etc. We are working with 2 Telcos and we are getting voice service.

3845 has 4 PRI ports. 2 of them are connected to Telcos and they are on the first VWIC2 card and the other 2 is connected to 3945 which is the main device for our IP Telephony.

Telco1----           -----
                 3845         3945
Telco2----           -----

I have the following commands for network clock:

network-clock-participate wic 0
network-clock-participate wic 1
network-clock-select 1 E1 0/0/0
network-clock-select 2 E1 0/0/1

Telco1 has no slip errors since it is the master clock source.

Telco2 has slip errors since we are using Telco1's clock

We can not use clock source line independent since this is a voice line.

3845 acts as network side for the connections between 3845 and 3945. We do have slip errors on these connections as well.

Unfortunately I do not have access to 3945 router.

Any ideas to get rid of slip errors?

Here is E1 controllers status:

E1 0/0/0 is up.
  Applique type is Channelized E1 - balanced
  No alarms detected.
  alarm-trigger is not set
  Version info Firmware: 20100222, FPGA: 13, spm_count = 0
  Framing is NO-CRC4, Line Code is HDB3, Clock Source is Line.
  Data in current interval (238 seconds elapsed):
     0 Line Code Violations, 0 Path Code Violations
     0 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins
     0 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
  Total Data (last 24 hours)
     0 Line Code Violations, 0 Path Code Violations,
     0 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins,
     0 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
E1 0/0/1 is up.
  Applique type is Channelized E1 - balanced
  No alarms detected.
  alarm-trigger is not set
  Version info Firmware: 20100222, FPGA: 13, spm_count = 0
  Framing is CRC4, Line Code is HDB3, Clock Source is Line.
  Data in current interval (239 seconds elapsed):
     0 Line Code Violations, 0 Path Code Violations
     30 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins
     30 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
  Total Data (last 24 hours)
     0 Line Code Violations, 0 Path Code Violations,
     10938 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins,
     10938 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
E1 0/1/0 is up.
  Applique type is Channelized E1 - balanced
  No alarms detected.
  alarm-trigger is not set
  Version info Firmware: 20100222, FPGA: 13, spm_count = 0
  Framing is NO-CRC4, Line Code is HDB3, Clock Source is Line.
  Data in current interval (238 seconds elapsed):
     0 Line Code Violations, 0 Path Code Violations
     84 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins
     84 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
  Total Data (last 24 hours)
     0 Line Code Violations, 0 Path Code Violations,
     30432 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins,
     30432 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
E1 0/1/1 is up.
  Applique type is Channelized E1 - balanced
  No alarms detected.
  alarm-trigger is not set
  Version info Firmware: 20100222, FPGA: 13, spm_count = 0
  Framing is NO-CRC4, Line Code is HDB3, Clock Source is Line.
  Data in current interval (239 seconds elapsed):
     0 Line Code Violations, 0 Path Code Violations
     53 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins
     53 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
  Total Data (last 24 hours)
     0 Line Code Violations, 0 Path Code Violations,
     4259 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins,
     4259 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs

 

 

 

 

 

 

 

 

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