If both ports are set as line, you will have 2 clocks driving the single Phase locked loop (PLL) clock recovery. This can sometimes lead to the PLL not being able to sync up to either clock reference and shows as slips on either of the ports.
A fix here is to can set the second port as clock source internal. The card's PLL will sync to the clock source on the first port, and use this recovered clock to drive the second port TX. Assuming both T1's are in sync externally, this will not cause any issues as the recovered clock being used to drive the TX on the second port is the same as the RX clock on this port.
If the two T1's are connected to dissimilar services that have different clocks then the only way to fix this is to use two single port cards or use the independent clock feature on the VWIC2 cards.
