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New Member

E1 timing issue

Hi,

I have an issue with slip secs on a 2811 with a VWIC-1MFT-E1 card, I have tried setting the clock source to internal as well as line but this issue remains, any ideas? thanks

E1 0/0/0 is up.

Applique type is Channelized E1 - balanced

No alarms detected.

alarm-trigger is not set

Version info Firmware: 20041023, FPGA: 16, spm_count = 0

Framing is CRC4, Line Code is HDB3, Clock Source is Internal.

CRC Threshold is 320. Reported from firmware is 320.

Data in current interval (574 seconds elapsed):

0 Line Code Violations, 0 Path Code Violations

14 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins

14 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs

Total Data (last 24 hours)

0 Line Code Violations, 0 Path Code Violations,

2530 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins,

2530 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs

3 REPLIES
VIP Purple

Re: E1 timing issue

Hello,

since slip secs are almost always clocking-related, and since you already have tested the only configurable options on your end, line and internal, I would check with the service provider and have them run a test to their DSU/CSU.

Regards,

GP

New Member

Re: E1 timing issue

I had a similiar issue with a T1 on a 2821. I added the "network-clock-select 1 t1 0/0/0" referencing my T1 controller and my slips went away. This is a global config command and it tells the backplane to derive clock from the controller you specify. You can do a 'show network-clocks' command to see what the current clock source is. By default it is the backplane.

Thanks,

Jason

Re: E1 timing issue

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