Sorry not to provide the answer. I've had many problems with this one. I used one of them as PRI for IP Telephony and the other one for Data. It's just that the router only lets me use one of them as clock reference with the network clock select priority etc.. command. I've been using always the one with the T1 PRI for clock reference as voice and faxes are more suceptibles to slips errors. This makes the router use the provider in this T1 as the clock reference for the dsp's and the backplane clock. I think that the slips in ths Data T1 are because of the difference in the clocks of the router and the provider sending the clocking in that Data T1. So I have the PRI T1 without slips errors and the Data T1 in the same 2MFT-T1 with lots of slips but working fine.
The vwic-2mft-t1 has only one pll according to the cisco SE I talked with. So the 2 port vwic module can not accept clock from both circuits. If these are point to point t1's then you as the customer provide clock on the circuits. If this is the case you can provide clock on both circuits from the vwic-2mft-t1 module. If not, ouch. I had to install a wic-1dsu-t1 to pick up the second frame-relay circuit. If this is a frame-relay or atm circuit you might call the provider and see if they will provide the same clock on both circuits.
That seems to be correct but what if the two T1's are for voice? How to set the clocking if can only get the clock from one of them. I've tried clock source internal etc... but nothing seems to work in this scenario.
When you using voice with either a first generation or second generation 2MFT-T1 you have to receive clock on one port (clock source line) and provide clock on the other port (clock source internal) and have the other side receive your clocking. The internal architecture of the ISR DSPs only allows a single clock source. Other solutions might be another router or NM-HDV with seperate DSPs? Contact TAC for further assistance.
The second generation MFT enhanced clocking support allows dual clock sources for data applications, as the card has dual PLLs.
The second generation has "Enhanced Clocking Support" which means dual PLLs for data applications with seperate clock sources. When used for voice DSPs can only have a single clock source, a limitation of the ISR architecture.
We are pleased to announce availability of Beta software for 16.6.3. 16.6.3 will be the second rebuild on the 16.6 release train targeted towards Catalyst 9500/9400/9300/3850/3650 switching platforms. We are looking for early feedback from custome...